Silicon & Systems Research
Indigenous edge-AI silicon, designed with agents
Drutam's research arm builds edge-AI accelerator IP and the system software around it — and pioneers an agentic methodology for silicon development itself.
The IP
The accelerator
Drutam's core IP is an edge-AI accelerator designed around systolic-array compute: INT8/INT16 matrix engines paired with FP32 vector processing. The architecture is prototyped and iterated on datacenter-class FPGAs today, and is engineered for a clean path to ASIC.
Systolic-array compute
INT8/INT16 matrix cores with FP32 vector processing.
FPGA-prototyped
Running on datacenter-class FPGAs; engineered for tape-out.
General tensor substrate
A programmable deep-learning core, not a fixed-function block.
Indigenous IP
Architected, verified, and iterated end-to-end in India.
The methodology
The agentic hardware flow
What distinguishes our silicon R&D is how the silicon is built. AI agents are embedded across the hardware development flow — drafting RTL from specification, generating and triaging verification, exploring synthesis and timing-closure strategies, iterating physical design.
The research output is therefore twofold: the accelerator IP itself, and a reusable agentic methodology for building silicon. We believe this methodology is itself a strategic capability for any nation building a semiconductor design workforce.
The platform
System software research
An accelerator is only useful when models actually run on it. The vertical spans compilers, runtimes, and instruction-set research for resource-constrained edge controllers — so our hardware ships as a usable platform, not a bare chip. The long-term arc is a complete edge-AI deployment platform: silicon, system software, and deployment tooling, designed together.
Continuity
Years in the making
- 01
Origins
Deep-learning accelerator research begins at IIT Madras with the ShaktiMAAN project.
- 02
Prototyping
Multi-year architecture iteration; the accelerator runs and is validated on datacenter-class FPGAs.
- 03
Agentic flow
AI agents embedded across RTL, verification, and physical-design exploration — in production use on our own silicon.
- 04
Ahead
ASIC realisation and a complete edge-AI deployment platform: silicon, system software, and tooling.
- Origin
- IIT Madras · ShaktiMAAN lineage
- Incubation
- IITM Pravartak Technologies Foundation
- Honorary Advisor
- Prof. V. Kamakoti
- Design
- Indigenous, end-to-end in India
Made in India 🇮🇳
Indigenous by design
Drutam's accelerator IP, agentic methodology, and system software are architected end-to-end in India — aligned with the national priority of building indigenous semiconductor design capability, edge-AI silicon, and a trained silicon-design talent pipeline.
Institutional & research partnerships
For government programmes, academic collaboration, and strategic partners in indigenous silicon — we welcome the conversation.